Aspects of the present invention relate generally to the field of integrated circuit design, and more specifically to pattern identification and classification.
Design rule based validation of integrated circuits has been accomplished with the assistance of a design rule check (DRC) process. The design rule check (DRC) process helps minimize manufacturing problems by ensuring that the circuit design abides by a set of detailed rules and parameters. During DRC, a layout is examined for violations of the defined design rules. When a circuit feature is located within the layout that violates a particular design rule, the violation is flagged or otherwise brought to the designer's attention.
However, the DRC process often uses design rules that are too constricting in order to conform to the “lowest common denominator” of acceptable layout design, and are otherwise difficult to implement correctly. Drafting or editing a set of design rules to avoid overly restricting design rules of more general applicability for each layout is time consuming and inefficient.
Accordingly, there is a need in the art for efficient identification of patterns in a complex layout such that the pattern based validation of a layout is scalable to a very large number of design rules and shape configurations.